Language:
English
繁體中文
Help
回圖書館
Login
Back
Switch To:
Labeled
|
MARC Mode
|
ISBD
Design and test technology for depen...
~
Vierhaus, Heinrich Theodor, (1951-)
Design and test technology for dependable systems-on-chip
Record Type:
Electronic resources : Monograph/item
Title/Author:
Design and test technology for dependable systems-on-chip/ Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors.
other author:
Ubar, Raimund,
Published:
Hershey, Pa. :IGI Global (701 E. Chocolate Avenue, Hershey, Pennsylvania, 17033, USA), : c2011.,
Description:
xxv, 550 p. :ill. ; : 29 cm.;
Subject:
Systems on a chip - Design and construction. -
Online resource:
http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/978-1-60960-212-3
ISBN:
9781609602147 (ebook)
Design and test technology for dependable systems-on-chip
Design and test technology for dependable systems-on-chip
[electronic resource] /Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors. - Hershey, Pa. :IGI Global (701 E. Chocolate Avenue, Hershey, Pennsylvania, 17033, USA),c2011. - xxv, 550 p. :ill. ;29 cm.
Includes bibliographical references.
Covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC).
Mode of access: World Wide Web.
ISBN: 9781609602147 (ebook)Subjects--Topical Terms:
133038
Systems on a chip
--Design and construction.Subjects--Index Terms:
Built-in self repair for logic structures
LC Class. No.: TK7895.E42 / D467 2011e
Dewey Class. No.: 621.3815
Design and test technology for dependable systems-on-chip
LDR
:01964nmm a2200397 a 4500
001
169768
003
IGIG
005
19991118134548.0
008
160302s2011 paua fsb 000 0 eng d
010
$z
2010045850
020
$a
9781609602147 (ebook)
020
$a
9781609602123 (hardcover)
020
$a
1609602129 (hardcover)
035
$a
(CaBNvSL)gtp00546193
035
$a
00000356
040
$a
CaBNvSL
$c
CaBNvSL
$d
CaBNvSL
050
4
$a
TK7895.E42
$b
D467 2011e
082
0 4
$a
621.3815
$2
22
245
0 0
$a
Design and test technology for dependable systems-on-chip
$h
[electronic resource] /
$c
Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors.
260
$a
Hershey, Pa. :
$c
c2011.
$b
IGI Global (701 E. Chocolate Avenue, Hershey, Pennsylvania, 17033, USA),
300
$a
xxv, 550 p. :
$b
ill. ;
$c
29 cm.
504
$a
Includes bibliographical references.
520
3
$a
Covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC).
538
$a
Mode of access: World Wide Web.
650
0
$a
Systems on a chip
$x
Design and construction.
$3
133038
650
0
$a
Networks on a chip
$x
Design and construction.
$3
241901
650
0
$a
Systems on a chip
$x
Testing.
$3
133216
650
0
$a
Networks on a chip
$x
Testing.
$3
240579
653
$a
Built-in self repair for logic structures
653
$a
Combined test-data compression and test planning
653
$a
Diagnostic modeling of digital systems
653
$a
Fault simulation and fault injection technology
653
$a
Fault-tolerant and fail-safe design based on reconfiguration
653
$a
Flexible fault-tolerant schedules for embedded systems
653
$a
Memory testing and self-repair
653
$a
Optimizing fault tolerance for multi-processor system-on-chip
653
$a
Software-based self-test of embedded microprocessors
653
$a
Transient faults detection and compensation
700
1
$a
Ubar, Raimund,
$d
1941-
$3
331199
700
1
$a
Raik, Jaan,
$d
1972-
$3
331200
700
1
$a
Vierhaus, Heinrich Theodor,
$d
1951-
$3
331201
710
2
$a
IGI Global.
$3
225644
776
0
$c
(Original)
$w
(DLC)2010045850
776
0 8
$i
Print version:
$z
1609602129
$z
9781609602123
$w
(DLC) 2010045850
856
4 1
$3
Chapter PDFs via platform:
$u
http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/978-1-60960-212-3
based on 0 review(s)
Multimedia
Reviews
Add a review
and share your thoughts with other readers
Export
pickup library
Processing
...
Change password
Login