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Verification and validation in syste...
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SpringerLink (Online service)
Verification and validation in systems engineering = assessing UML/SysML design models /
Record Type:
Electronic resources : Monograph/item
Title/Author:
Verification and validation in systems engineering/ by Mourad Debbabi ... [et al.].
Reminder of title:
assessing UML/SysML design models /
other author:
Debbabi, Mourad.
Published:
Berlin, Heidelberg :Springer-Verlag Berlin Heidelberg, : 2010.,
Description:
xxvi, 248 p. :ill., digital ; : 24 cm.;
Contained By:
Springer eBooks
Subject:
Management of Computing and Information Systems. -
Online resource:
http://dx.doi.org/10.1007/978-3-642-15228-3
ISBN:
9783642152283 (electronic bk.)
Verification and validation in systems engineering = assessing UML/SysML design models /
Verification and validation in systems engineering
assessing UML/SysML design models /[electronic resource] :by Mourad Debbabi ... [et al.]. - Berlin, Heidelberg :Springer-Verlag Berlin Heidelberg,2010. - xxvi, 248 p. :ill., digital ;24 cm.
ISBN: 9783642152283 (electronic bk.)Subjects--Topical Terms:
120422
Management of Computing and Information Systems.
LC Class. No.: TA168 / .V47 2010
Dewey Class. No.: 620.001171
Verification and validation in systems engineering = assessing UML/SysML design models /
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assessing UML/SysML design models /
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Computer Science (Springer-11645)
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